The invention relates to a circuit arrangement for the recognition of faults occurring in circuit assemblies. Such faults are indicated in each case through the emission of a fault signal and may be either static faults persisting for more than a predetermined first time span or dynamic faults which do not exceed a predetermined second time span, in a central control unit that is connected with these circuit assemblies and drives them for the emission of data signals, particularly in a microprocessor assembly.
If, in a circuit arrangement having a central control unit and a number of circuit assemblies connected with it, the fault control procedure that is necessary when faults occur takes place in the central control unit, then it is advantageous for effective fault control, if a distinction can be made in the central control unit between static and dynamic faults which occur in the circuit assemblies. Depending on the kind of fault that has occurred in each case, different measures will, in general, have to be initiated from the central control unit to control the faults. For example, the presence of a static fault in one of the circuit assemblies may result in this faulty circuit assembly being taken out of service by the central control unit, while the other fault-free circuit assemblies continue to operate without any change. On the other hand, in the presence of a dynamic fault, a statistical evaluation of the fault can first be carried out. Depending on the result of this evaluation in each case, appropriate measures to eliminate the fault will then be initiated by the central control unit. These measures may again include removing the faulty circuit assembly from operation.